Secure hardware devices, or “secure containers,” often utilize a persistent memory for storing state across power outages or failures. The Trusted Platform Module is one such secure container that utilizes a persistent memory. However, standard implementations of persistent memory, such as flash memory and non-volatile random access memory (NVRAM) have at least two disadvantages. First, these memory types are slow in terms of both latency and throughput. In addition, these memory types are write-cycle limited, meaning that they have a limit on the count of write cycles that they can perform.
The slowness and write-cycle limitations of persistent memory have led to the creation of techniques for building fast, non-write-cycle limited persistent memory. One approach for constructing such a memory uses RAM as a cache for NVRAM-backed storage. During normal operation, components of a computing device are able to read and write to the RAM, which is fast and has no write-cycle limitations. When power is lost, the contents of RAM are flushed to the NVRAM. To provide short-term power for the flushing procedure, these techniques may employ a capacitor to write the contents from RAM to the NVRAM. The capacitor is charged when power is applied to the system, and is discharged by the circuitry that writes the RAM contents to NVRAM.
However, in a straightforward application to a system in which the memory should remain secure, the capacitor must be contained within the secure componentry. If the capacitor resides elsewhere, an attacker can subvert the system by disengaging the capacitor at a critical moment. However, if the size of the memory is substantial, the required capacitor may be too large to affordably house the capacitor within the secure componentry.